library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Demo is port ( Clk : in std_logic; ResetN : in std_logic; TasteN1 : in std_logic; Led : out std_logic_vector(7 downto 0) ); end entity; architecture Demo_Arch of Demo is type states is(Reset, LedOnLow, LedOnHigh, LedAllOn); signal state : states; signal TasteN1_old : std_logic; — flipflop — signal […]
Category Archives: VHDL
FPGA Workshop
S-RAM based 22k Logic Cells Lookup-Table, 16 in, FlopFlop, 1 out Programmierbare Interconnection Points. 2 Programmiermethoden – Struktural, auf Hardwareebene (1980) – Verhaltensbasiert, Funktional (Verilog) Programmiert wird: – Lookup Table – Startwert vom FlipFlop – Interconnection points Seither weiterentwicklung: – RAM (512k) in 9k Blöcken – PLLs, gut, wenig jitter – Hardware Multiplier – keine […]